안녕하세요.
삼성의 차기(?) SoC로 예상되는 GH7에 대한 내용이 있어서 공유합니다.
메일링으로 커밋된 정보를 보면 엑시노스라고 하지 않고 GH7이라고 이름 붙였고,
DTSi를 보면 4개의 Core가 arm, armv8, timer에도 arm,armv8 이라고 되어 있습니다.
64비트인 ARMv8이 조금씩 들어나고 있네요. 물론 시간이 조금 더 지나면 더욱 많은 정보가 들어나겠지요. ㅎㅎ
diff --git a/arch/arm64/boot/dts/samsung-gh7.dtsi b/arch/arm64/boot/dts/samsung-gh7.dtsi new file mode 100644 index 0000000..5b8785c --- /dev/null +++ b/arch/arm64/boot/dts/samsung-gh7.dtsi @@ -0,0 +1,108 @@ +/* + * SAMSUNG GH7 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; + +/memreserve/ 0x80000000 0x0C400000; + +/ { + model = "SAMSUNG GH7"; + compatible = "samsung,gh7"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; +
+
+ gic: interrupt-controller@1C000000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x1C001000 0 0x1000>, /* GIC Dist */
+ <0x0 0x1C002000 0 0x1000>, /* GIC CPU */
+ <0x0 0x1C004000 0 0x2000>, /* GIC VCPU Control */
+ <0x0 0x1C006000 0 0x2000>; /* GIC VCPU */
+ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xff01>, /* Secure Phys IRQ */
+ <1 14 0xff01>, /* Non-secure Phys IRQ */
+ <1 11 0xff01>, /* Virt IRQ */
+ <1 10 0xff01>; /* Hyp IRQ */
+ clock-frequency = <100000000>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 294 8>,
+ <0 295 8>,
+ <0 296 8>,
+ <0 297 8>,
+ <0 298 8>,
+ <0 299 8>,
+ <0 300 8>,
+ <0 301 8>;
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ serial@12c00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12c00000 0x10000>;
+ interrupts = <418>;
+ };
+
+ serial@12c20000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12c20000 0x10000>;
+ interrupts = <420>;
+ };
+ };
+};
.
