Chisel 사용법에 대한 정보를 하기와 같이 공유합니다.

▣ Chisel 3 설치

         >>> Installation

                 ▶ Overview

                        ⊙ Chisel3 (Scala) to Firrtl (this is your "Chisel RTL").
                        ⊙ Firrtl to Verilog (which can then be passed into FPGA or ASIC tools).
                        ⊙ Verilog to C++ for simulation and testing using Verilator.

▣ Chisel Tutorials (Release branch)

         >>> Getting the Repo

$ git clone https://github.com/ucb-bar/chisel-tutorial.git
$ cd chisel-tutorial
$ git fetch origin
$ git checkout release

Note: ./run-problem.sh, ./run-solution.sh, ./run-examples.sh are convenience scripts to invoke tests

▣ The Basics

>>> Running the Chisel Simulation
     $ ./run-examples.sh GCD

                  or
     $ ./run-examples.sh all

>>> Generating Verilog

     $ ./run-examples.sh GCD --backend-name verilator

                  or
     $ ./run-examples.sh all --backend-name verilator

      ▷ GCD.v - Verilog representation of the Chisel circuit,

      ▷ GCD.vcd - waveform dump of the circuit signals during the simulation.