[커널 18차] 9주차

2021.07.29 20:15

Runixs 조회 수:256

 

2021/07/24 스터디 9차

 

1) 입장하신 분들은 오후 3:00 시작전까지 참가자명을 한글 실명으로 변경.

2) 출첵을 위해 구글 문서의 다음 참석 항목에 성함을 기록.

    jake.dothome.co.kr 에 링크가 있습니다.

3) 접속 후 3시 정각에 웹캠 on.

참석

  • 36명 참석(문영일, 최영민, 최준근, 권효만, 정동훈, 류호은, 황성민, 장철연, 이정재, 정은식, 문연수,임채훈, 송기원, 이재훈, 김준영, 김성준, 송준영, 지영근, 정주희, 안이수, 차민희, 민호기, 이한솔, 한동수,유민호,서민혁, 강혁, 박진현, 이일영, 김각래, 안유빈, 최서정, 김정임, 이민욱, 김경인, 최영민) 

진도 및 내용

  • 서기: 

  • 이번주 진도: 

    • ARMv8-A Programmers Guide 책 ~p161

  • 다음주 진도: 

    • ARMv8-A Programmers Guide 책 - MMU - p162

  • 코드 진행: 문연수


 

Q. T32를 쓰는 경우.

 

Programmer’s Guide for ARMv8-A

Chapter 1 Introduction

ARMv7-A : Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9, Cortex-A15, and Cortex-A17

ARMv8-A : Cortex-A53(리틀코어), Cortex-A57(빅코어), Cortex-A72, Cortex-A73

 

Chapter 2 ARMv8-A Architecture and Processors

 

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2.2 ARMv8-A Processor properties

 

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Cortex-A57 특징

 Out-of-order(최적화에 따라 실행 순서를 변경할수 있다.), 15+ stage pipeline.

 

Chapter 3 Fundamentals of ARMv8

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Chapter 4 ARMv8 Registers

 

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Chapter 5 An Introduction to the ARMv8 Instruction Sets

Chapter 6 The A64 instruction set

  • Data Memory Barrier (DMB). This forces all earlier-in-program-order memory accesses to become globally visible before any subsequent accesses.

  • Data Synchronization Barrier (DSB). All pending loads and stores, cache maintenance instructions, and all TLB maintenance instructions, are completed before program execution continues. A DSB behaves like a DMB, but with additional properties.

  • Instruction Synchronization Barrier (ISB). This instruction flushes the CPU pipeline and prefetch buffers, causin

 

Chapter 7 AArch64 Floating-point and NEON

 

Chapter 8 Porting to A64

 

Chapter 9 The ABI for ARM 64-bit Architecture

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Chapter 10 AArch64 Exception Handling

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10.4 AArch64 exception table


 

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Q. Current EL with SP0 에 대한 해석은?

> EL0는 same exception level로 이동 X. EL1, 2, 3인데 SP0를 쓰는 상황은?

> SP_EL0는 kernel task stack을 가르킨다.





 

Chapter 11 AArch64 Cache

 

L1 cache에는 dirty bit가 없다.

SCU: CPU가 무엇을 하는지 snooping

 

x0 = 시작 주소

x1 = 길이

x2 = 캐시 라인 사이즈 (바이트)=0x20

x3 = 캐시 라인 사이즈 -1=0x1f

 

Point of Unification

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Knowledge of the PoU enables self-modifying code to ensure future instruction fetches are correctly made from the modified version of the code. They can do this by using a two-stage process:

  • Clean the relevant data cache entries by address.

  • Invalidate instruction cache entries by address.

The ARM architecture does not require the hardware to ensure coherency between instruction caches and memory, even for locations of shared memory.

 

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https://developer.arm.com/documentation/ihi0056/c


 

https://developer.arm.com/documentation/ddi0595/2021-03/AArch64-Registers/SCTLR-EL1--System-Control-Register--EL1-?lang=en#fieldset_0-11_11-1

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